Write a λ-term and watch it become a net of interaction combinators. Red wires are active pairs. Click any of them to rewrite it: each rewrite only touches its own neighbourhood.
Type \ for λ
γ constructor. λ and @ are the same agent, facing different ways.
δ duplicator. Shares a value that is used more than once.
ε eraser. Removes a value that is never used.
Active pair: two principal ports meet. Click to rewrite.
Click a red wire
0 / 0
Step rewrites one pair. Round rewrites every active pair at once, the way separate units would in parallel. The demo engine is plain symmetric interaction combinators with labelled duplicators, not the S8S rule set.
Work queue
Active redexes
0
Work
0
Span
0
Utilization
0%
Placeholder values
1 of 4
One RXU
Three properties of one design.
Universal
Removes
The accelerator archipelago: a different chip, language and toolchain for every kind of work.
How
One architecture and one language for logic, graphs and numerical work.
Evidence
Designed
Inspect the claim
Question card placeholder: “Does general mean equally fast on every workload?” Short verdict, mechanism, evidence level.
Accessible
Removes
Semantic fracture: intent lost between language, compiler, ISA and hardware.
How
Functional semantics are the machine's native form, so programs can be checked formally.
Evidence
Designed
Inspect the claim
Question card placeholder: “Do I have to learn a new language?” Short verdict, mechanism, evidence level.
High-performance
Removes
The movement and coordination tax: state shuttled across memory levels and devices.
How
State sits beside the logic that rewrites it; independent pairs rewrite in parallel as units are added.
Evidence
SimulatedProjected
Inspect the claim
Question card placeholder: “Does scaling stay linear once traffic crosses chips?” Short verdict, mechanism, evidence level.
If one design unifies so much, why isn't the world already running on it?
Because it still has to be built. Scroll to follow the road.
Team
Cheng Peng
Co-founder
Fundraising, product narrative, partnerships, IP strategy and building the organization.
Jiahong Ye
Co-founder
System architecture, compiler work, FPGA implementation and technical execution.
Who we're looking for
Senior hardware engineer: RTL, FPGA, verification
Full-stack and developer tooling
Formal methods and PL researchers
Workload experts with irregular, graph-shaped problems